The growth of information processing apparatus, such as computers, has resulted in an increase in the need for high-speed operation and large-capacity in semiconductor memory devices employed as important components of the information processing apparatus.
Nonvolatile semiconductor memory device, such as flash EEPROM (electrically erasable programmable read only memory) etc., are being widely used as a data storage device of portable electronic systems. A NAND flash semiconductor memory device having a memory cell array of NAND cells is well known in the field as a memory that has a relatively high degree of memory cell integration and is flash-erasable. In this flash semiconductor memory device a high voltage, e.g., 15V through 20V, relatively higher than power source voltage, is typically applied to a selected word line during a programming operation.
A high voltage should be used in the nonvolatile semiconductor memory device in order to erase or program data through a well-known F-N tunneling or channel hot electron injection method. Typically, the high voltage to be used in the nonvolatile semiconductor memory device may be applied through an external pin of a chip or may be generated internally within a chip. Generally, in generating the high voltage within the chip, a high voltage generating circuit containing a high voltage pump or charge pump for performing a charge pumping operation is employed in the chip. An example of a circuit for the generation of a high program voltage is disclosed in, e.g., U.S. Pat. No. 5,889,720.
FIG. 1 illustrates a use of high voltage pump in a conventional semiconductor memory device. Referring to FIG. 1, a high voltage generated in the high voltage pump 2 is applied to a peripheral circuit 4 provided within a chip through an output line L1. The peripheral circuit 4 may be provided as a functional block for selectively applying high voltage to a word line, like a row line level selection unit etc. in a nonvolatile semiconductor memory device. An exemplary embodiment of the high voltage pump 2 is illustrated in FIG. 2.
Referring to FIG. 2, a plurality of MOS transistors MP1,MN1–MNn and a plurality of capacitors C1–Cn have a mutually connected configuration. Operation of the charge pump in the high voltage pump 2 of FIG. 2 is described as follows.
When a pump enable signal nPUMPen for a charge supply is enabled as a low state and a first phase control signal P1 and a second phase control signal P2 are applied as mutually exclusive pulse signals; a charge pumping operation for the generation of high voltage starts. That is, a charge supply transistor MP1 is turned on to apply power source voltage to a node NT0, and the first phase control signal P1 has a high state and the second phase control signal P2 has a low state, then a first charge transfer transistor MN1 is turned on. The charge flowing in the node NT0 is transferred to a node NT1. The amount of the charge transferred to the node NT1 is increased by an operation of a first capacitor C1. Then, when the first phase control signal P1 is transited to a low state and the second phase control signal P2 is transited to a high state, a second charge transfer transistor MN2 is turned on to again increase the charge amount of the node NT1 and to transfer it to a node NT2. In this case a gate voltage of the first charge transfer transistor MN1 has transitioned to the low state, thus the charge of the node NT1 does not flow backward to the node NT0. This operation is consecutively performed in the charge transfer transistors that are connected with one another in series, then the pumped charge is transferred to an output terminal. The pumped high voltage higher than power source voltage is generated in a pumping output terminal Vpump provided as a source terminal of a final charge transfer transistor MNn.
A level of the high voltage generated in the pumping output terminal Vpump of the high voltage pump shown in FIG. 2 increases in sections where the phase control signal becomes high, and decreases by a predetermined level in sections where the phase control signal is maintained as a low state. Thus a voltage ripple may be generated as shown in a waveform RS of FIG. 4.
The ripple may need to be removed if the apparatus needs a uniform high voltage. In removing the voltage ripple it may be difficult to employ a ripple removing device given the level of integration of a semiconductor memory. That is, it may be necessary to use a ripple removing device of a smaller size than may be sufficient to withstand the high voltage of the pumping output terminal when the output terminal is disabled.
Furthermore, a typical pumping output terminal is provided with a specific discharge circuit for discharging the high voltage when the high voltage pump is disabled, but the specific discharge circuit may also limit or be limited by the level of integration.